#define GPFCONF  (*(volatile unsigned short*)0x56000050)
#define GPF1_MASK (0x3 << 2)
#define GPF4_MASK (0x3 << 8)
#define GPF2_MASK (0x3 << 4)
#define GPF0_MASK (0x3 << 0)

#define GPF1_AS_INT (0x2 << 2)
#define GPF4_AS_INT (0x2 << 8)
#define GPF2_AS_INT (0x2 << 4)
#define GPF0_AS_INT (0x2 << 0)

#define EINTMASK  (*(volatile unsigned long*)0x560000a4)
#define INTMSK    (*(volatile unsigned long*)0x4a000008)

void close_watch_dog() {
    unsigned long* pwatchdog = (unsigned long*)0x53000000;
    *pwatchdog = 0;
    return;
}

void init_sdram() {
#define SDRAM_REG_BASE 0x48000000
    int i = 0;
    unsigned long* pIt = (unsigned long*)SDRAM_REG_BASE;
    unsigned long reg_value_arr[] = {
            0x22011110,
            0x700,
            0x700,
            0x700,
            0x700,
            0x700,
            0x700,
            0x00018005,
            0x00018005,
            0x008c07A3,
            0xB1,
            0x30,
            0x30
    };
    for(i = 0; i < 13; ++i) {
        *pIt = reg_value_arr[i];
        ++pIt;
    }
    return;
}


void init_irq() {
    //step1:config key as interupt
//    //config key1 as Interupt
//    GPFCONF &= ~GPF1_MASK;
//    GPFCONF |= GPF1_AS_INT;
//
//    //config key2 as Interupt
//    GPFCONF &= ~GPF4_MASK;
//    GPFCONF |= GPF4_AS_INT;
//
//    //config key3 as Interupt
//    GPFCONF &= ~GPF2_MASK;
//    GPFCONF |= GPF2_AS_INT;
//
//    //config key4 as Interupt
//    GPFCONF &= ~GPF0_MASK;
//    GPFCONF |= GPF0_AS_INT;
    /*
     * MASK:
     *  00   00   00   11   00   11   11   11
     * GPF7 GPF6 GPF5 GPF4 GPF3 GPF2 GPF1 GPF0
     * 0x  0         3         3         F
     *
     * VAL:
     *  00   00   00   10   00   10   10   10
     * GPF7 GPF6 GPF5 GPF4 GPF3 GPF2 GPF1 GPF0
     * 0x  0         2         2         A
     *
     * */
#define GPF1_4_2_0_MASK 0x033F
#define GPF1_4_2_0_AS_INT 0x022A
    GPFCONF &= ~GPF1_4_2_0_MASK;
    GPFCONF |= GPF1_4_2_0_AS_INT;
//    GPFCONF = GPF1_4_2_0_AS_INT;



    //step2:clear interupt mask bit
//    //key1:clear EINT1 mask bit
//    INTMSK &= ~(1 << 1);
//
//    //key2:INT4 MASK bit clear
//    EINTMASK &= ~(1 << 4);
//    INTMSK &= ~(1 << 4);
//
//    //key3:clear EINT2 mask bit
//    INTMSK &= ~(1 << 2);
//
//    //key4:clear EINT0 mask bit
//    INTMSK &= ~(1 << 0);
    EINTMASK &= ~(1 << 4);

    /* INTMSK:
     * ...  nBATT_FLT INT_CAM EINT8_23 EINT4_7 EINT3 EINT2 EINT1 EINT0
     *bit         7      6        5       4      3     2     1     0
     *mask_vlaue  0      0        0       1      0     1     1     1
     *mask_vlaue  0x17
     */
    INTMSK &= ~(0x17);

    //step3: set interupt priority
    //config as default..
}










